The simplest way to understand Huawei’s latest semiconductor announcement is this: China is no longer only trying to catch up by buying the same tools as TSMC and Samsung. It is trying to change the rules of the race. If EUV lithography is blocked, Huawei’s answer is to reduce signal delay, shorten wiring, and stack logic vertically. In other words, if China cannot use the thinnest brush, it is trying to redesign the canvas.

Since the U.S.-China trade war began in 2018, semiconductors have become the central battlefield of technology competition. For China, chips are no longer just industrial components. They are the foundation of AI, defense, smartphones, telecom networks, electric vehicles, industrial automation, and national security.

This is why Xi Jinping’s semiconductor self-reliance campaign became so important. China understood that it could not become a durable manufacturing superpower if the most advanced chips, lithography tools, design software, and memory technologies remained controlled by the U.S. and its allies.

Huawei’s new roadmap must be read in that context. It is not just a technical announcement. It is a sanctions-response strategy.

Huawei is not saying it has defeated EUV today. It is saying China needs another path if EUV remains unavailable.

The 2018 turning point: chips became geopolitical weapons

December 1, 2018 has become a symbolic date in the semiconductor cold war. Several major events happened on the same day or around the same moment.

ASML’s supplier Prodrive suffered a fire that delayed some lithography equipment deliveries. Huawei CFO Meng Wanzhou was arrested in Canada on a U.S. extradition request. Stanford physicist Zhang Shoucheng died, with his family describing it as an apparent suicide after depression. At the same time, Donald Trump and Xi Jinping were meeting at the G20 summit in Argentina to negotiate a trade-war truce.

These events should not be treated as proven parts of one coordinated plot. The confirmed facts are that they occurred in the same geopolitical environment: U.S.-China tensions were rising, Huawei was under legal and national-security pressure, and China’s access to advanced semiconductor technology was becoming a strategic issue.

The most important structural event was the EUV blockade. EUV lithography is essential for the most advanced semiconductor manufacturing. ASML is the only company capable of supplying commercial EUV systems. China’s SMIC had sought access to EUV tools, but Dutch export licensing later prevented EUV shipment to China under U.S. pressure.

From that point, China faced a hard ceiling. It could still use DUV lithography and multi-patterning techniques, but without EUV, advanced-node production becomes more expensive, more complex, and lower-yield.

The EUV blockade did not stop China from making chips. It made every advanced chip harder, slower, costlier, and less efficient to manufacture.

Why EUV matters so much

Modern semiconductor scaling has traditionally depended on making patterns smaller. The smaller the transistors and wiring structures become, the more computing elements can fit into the same area. This improves density, speed, and power efficiency.

EUV lithography is like an extremely fine brush. It allows chipmakers to draw much smaller patterns on silicon wafers. TSMC, Samsung, and Intel use EUV to make advanced chips at leading-edge process nodes.

DUV lithography is an older tool. It can still be pushed very far through multi-patterning, but that requires repeating exposure and etching steps many times. Each extra step increases cost, complexity, error risk, and yield loss.

This is why Huawei and SMIC can produce advanced chips, but not with the same efficiency as TSMC using modern EUV-based production. They can sometimes get near the target, but the cost and yield problem remains.

In simple terms, China can still paint with a thicker brush. But making a fine pattern with a thick brush takes more skill, more time, and more failed attempts.

Huawei’s answer: Tau Scaling Law

At IEEE ISCAS 2026 in Shanghai, Huawei’s He Tingbo presented Tau Scaling Law. The basic idea is to shift the focus from geometric scaling to time scaling.

In semiconductor design, tau can be understood as the time delay involved in signal movement. A chip does not only depend on how small its transistors are. It also depends on how quickly signals can move through the circuit.

Traditional Moore’s Law focuses on shrinking transistors and increasing density. Huawei’s Tau Scaling proposal says the industry should also focus on reducing signal delay by changing architecture, wiring, layout, and system design.

This is a practical response to sanctions. If Huawei cannot easily shrink transistor features with EUV, then it must improve performance through other means. Shorter wires, faster signal paths, better packaging, 3D integration, and system-level optimization become more important.

Huawei’s Tau Scaling is essentially saying: stop measuring progress only by how small the transistor is. Measure how fast the signal completes useful work.

LogicFolding: stacking instead of only shrinking

LogicFolding is the architectural concept that makes Huawei’s strategy easier to visualize. Instead of laying logic circuits flat across a two-dimensional plane, Huawei wants to fold and stack logic structures vertically.

A useful analogy is housing. TSMC and Samsung continue to make the “houses” smaller and smaller on a flat piece of land. Huawei is saying that if the houses cannot be shrunk enough, it can build upward like an apartment building.

The benefit is shorter wiring distance. When two circuit elements are far apart on a flat layout, signals must travel through longer interconnects. Longer interconnects create delay, resistance, capacitance, and power loss.

If logic blocks are stacked and connected vertically, some signal paths can become shorter. That can reduce delay and improve performance even if the physical transistor process is not as advanced as TSMC’s or Samsung’s.

This is why LogicFolding matters. It tries to compensate for the lack of EUV by changing chip architecture.

The 1.4nm claim needs careful reading

Huawei’s 2031 target is described as reaching 1.4nm-equivalent density or performance. That wording matters.

It does not necessarily mean Huawei will manufacture a conventional physical 1.4nm process like TSMC’s A14 node. It means Huawei is aiming to use architectural techniques to reach performance or density comparable to what the industry associates with a 1.4nm-class node.

This distinction is important because process-node names are already partly marketing terms. A “3nm” or “2nm” node does not mean every transistor feature literally measures 3nm or 2nm. But even within that reality, there is still a difference between true leading-edge lithography-based scaling and architectural equivalence claims.

TSMC is expected to pursue real A14-class production using its advanced manufacturing ecosystem. Huawei is trying to reach a comparable outcome through a different route.

So the right interpretation is not “Huawei has already beaten TSMC.” The right interpretation is: Huawei has announced a technical route designed to reduce the damage from EUV restrictions.

Huawei’s 1.4nm roadmap is best understood as a 1.4nm-equivalent ambition, not proof that China already has a conventional 1.4nm manufacturing process.

Why this matters for China’s semiconductor independence

China’s semiconductor weakness is not only one missing machine. It is an ecosystem problem.

Advanced chipmaking requires lithography, etching, deposition, ion implantation, metrology, inspection, photoresists, EDA software, packaging, materials, process know-how, and high-yield manufacturing. The U.S. and its allies control critical parts of this chain.

Huawei’s strategy is therefore not limited to chip design. It is part of a wider attempt to build a self-reliant semiconductor ecosystem.

LogicFolding also requires new design tools. Reports say Peking University researchers have built prototype EDA tools tailored to Huawei’s LogicFolding architecture. That matters because ordinary chip-design software was built mostly around traditional 2D and multi-die 3D approaches.

If Huawei wants to build true intra-chip 3D logic structures, it needs software that can design, simulate, verify, and optimize those structures. Without domestic EDA capability, the architecture cannot scale.

This is where China’s challenge remains large. Prototype tools are not the same as commercial-grade EDA platforms. Turning academic prototypes into reliable industrial tools can take years.

The biggest technical problem: heat

The biggest technical question for LogicFolding is heat. When logic circuits are stacked vertically, heat becomes harder to remove.

In a flat chip, heat can spread toward the package and cooling system more directly. In a 3D logic structure, inner layers can become trapped between other active layers. That can create hot spots.

Heat is not a minor issue. Higher temperatures increase leakage current, reduce efficiency, hurt reliability, and limit clock speed. If heat is not controlled, the theoretical benefit of shorter wiring can be reduced or lost.

Huawei’s strategy therefore depends not only on circuit design but also on thermal design, packaging, materials, interconnects, and cooling.

This is why the market should not judge the roadmap only by transistor-density claims. Real-world performance depends on yield, heat, power consumption, reliability, manufacturability, and cost.

In 3D logic chips, the enemy is not only lithography. It is heat.

The second problem: yield and cost

The second problem is yield. More complex chip structures usually create more failure points. If a chip has more layers, more vertical connections, more alignment requirements, and more process steps, the probability of defects can rise.

This is already a challenge for China’s current advanced chips. DUV-based advanced-node production can work, but the process is more complex than EUV-based production. Complexity lowers yield. Low yield raises cost.

LogicFolding may improve some performance constraints, but it may also introduce new manufacturing risks. The economic question is therefore simple: can Huawei produce these chips at acceptable yield and cost?

A chip that works in a lab is one thing. A chip that can be mass-produced reliably in millions of units is another.

This is why the first commercial products matter. If the technology appears in future Kirin smartphone processors, the market can observe heat, battery life, performance, production volume, and user experience.

Why Huawei may test it first in smartphones

Smartphone chips are a logical testing ground. Huawei controls both hardware and software in its own ecosystem. It can optimize the chip, operating system, power management, and user experience together.

If LogicFolding-related techniques appear in Kirin processors, Huawei can test whether the architecture delivers enough performance improvement without unacceptable heat or battery drain.

But smartphones are also unforgiving. A phone has limited battery capacity, limited cooling space, and strict thermal constraints. If the chip runs too hot, users will notice quickly. The phone may throttle performance, battery life may decline, and reviews will expose the weakness.

This makes future Huawei Mate-series products important. Even if yield data remains secret, thermal behavior and real-world performance will be visible.

The key question is not only whether Huawei can make the chip. It is whether the chip can perform consistently inside a consumer device.

Why this matters for AI chips

The larger target is not only smartphones. The larger target is AI.

China wants domestic alternatives to Nvidia GPUs. Huawei’s Ascend AI chips are central to that effort. But AI accelerators require huge compute density, memory bandwidth, interconnect performance, and energy efficiency.

If Huawei can use Tau Scaling and LogicFolding to improve performance without relying on EUV, it could strengthen China’s domestic AI hardware ecosystem.

That would matter geopolitically. U.S. export controls aim to slow China’s access to the most advanced AI chips. China’s response is to build domestic substitutes, even if they are less efficient at first.

The question is whether China can close enough of the gap for domestic AI training and inference needs. It does not need to beat Nvidia globally immediately. It needs to support Chinese cloud providers, government projects, telecom systems, defense-related computing, and industrial AI without being fully dependent on U.S.-controlled supply chains.

Huawei’s chip strategy is not only about phones. It is about giving China a domestic AI hardware path under sanctions.

Why the U.S. should still take this seriously

It would be a mistake to dismiss Huawei’s roadmap as propaganda. It would also be a mistake to accept it as already proven.

The correct approach is to treat it as a serious strategic signal. Huawei is showing how it intends to move if EUV remains blocked. China is not waiting passively for sanctions to disappear. It is investing in alternative architectures, domestic tools, advanced packaging, and system-level optimization.

U.S. export controls can slow China. They can raise costs. They can delay access to leading-edge performance. But they also force China to concentrate resources on substitutes.

That is the long-term risk for the U.S. If sanctions eventually push China into building a workable domestic stack, the West may lose some of its leverage.

The timing matters. TSMC and Samsung still have large advantages in process technology, yield, tools, supplier relationships, and manufacturing experience. Huawei’s 2031 target is not an immediate threat to TSMC’s 2028 A14 roadmap. But it shows China is building a long game.

What to watch next

The first thing to watch is whether Huawei actually ships Kirin processors using LogicFolding-related techniques. Product-level performance will reveal more than conference slides.

The second is heat and battery life. If the new architecture runs hot or throttles under load, the market will know quickly.

The third is yield. Huawei and SMIC may not disclose yield data, but production volume, product availability, pricing, and teardown analysis can provide indirect signals.

The fourth is EDA development. LogicFolding needs specialized design tools. Watch whether Chinese universities and EDA firms can turn prototypes into industrial software.

The fifth is AI-chip application. If the same architecture moves from Kirin smartphone chips into Ascend AI accelerators, the strategic meaning becomes much larger.

The sixth is U.S. policy. If Washington tightens restrictions further, China may accelerate alternative architectures and domestic equipment investment.

The seventh is TSMC’s A14 progress. If TSMC executes its 1.4nm-class roadmap on schedule, Huawei’s 2031 equivalence target still leaves a meaningful gap.

Conclusion: China is trying to change the scaling game

Huawei’s Tau Scaling Law and LogicFolding announcement does not mean China has suddenly solved every semiconductor problem. It does not mean EUV no longer matters. It does not mean Huawei has already caught TSMC.

But it does show something important. China understands that copying the existing advanced-node path is difficult under export controls. Therefore, Huawei is trying to create another route: shorten signal paths, stack logic, reduce delay, redesign chip architecture, and build domestic tools around that strategy.

The concept is technically plausible. The hard part is execution. Heat, yield, cost, EDA maturity, packaging, and mass production will decide whether the idea becomes a real semiconductor breakthrough or only a clever workaround with limited commercial value.

The simplest way to read Huawei’s 1.4nm roadmap is this: China has not escaped the EUV blockade yet, but it is trying to build a semiconductor path where performance comes from architecture as much as lithography.